Hardware and Embedded Systems (HES) Group Computer Systems Lab (CSL), ELIS, Ghent University

Hardware and Embedded Systems (HES) Group

The Hardware and Embedded Systems (HES) Group is part of the Computer Systems Lab (CSL) at the ELIS Department, Ghent University.
Our work addresses electronic design automation and architectural challenges for FPGAs and ASICs, from logic synthesis and physical design to architecture exploration and system design.

Announcements

FPL 2026 in Ghent

FPL 2026 in Ghent

The 36th International Conference on Field-Programmable Logic and Applications (FPL 2026) will be held in Ghent, Belgium.

FPL is a leading international conference on field-programmable logic and reconfigurable computing, bringing together researchers and practitioners from academia and industry.

Prof. Dirk Stroobandt serves as General Chair and Dr. Poona Bahrebar as General Co-Chair of FPL 2026. FPL returns to Ghent for the second time, following the successful FPL 2017 conference also hosted by our group.

News

Call for Master Thesis Students

The HES group is looking for motivated master students interested in working on cutting-edge topics in FPGA design, electronic design automation, and hardware architectures.

Paper Accepted in Micro and Nanostructures

Our paper “Modeling and Optimization of CFET Structures for Sub-3 nm CMOS Scaling” by Nour El I Boukortt and Dirk Stroobandt has been accepted for publication in Micro and Nanostructures (Elsevier).

Highlights

Research

Research

Our group conducts research at the intersection of logic synthesis, physical design, and architecture exploration, with a particular emphasis on FPGA-based systems and emerging computing platforms.

Projects

Projects

We develop open-source tools and methodologies for FPGA design automation, including interconnect-aware synthesis, routing, and multi-die architectures.

People

People

Our team consists of faculty members, postdoctoral researchers, PhD students, and master’s students working collaboratively on advanced hardware and system-level design challenges.