Projects
Current Projects
The website of the Flanders Chips Competence Center, a consortium created between 4 Flemish Universities proposed under the European Chips Act to support the Flemish Industry. FC3 is co-funded by the European Union. The project is supported by the CHIPS JU and its members (including top-up funding by VLAIO).
Past Research Topics
1. Run-time Reconfiguration
Our group is world-renowned for its pioneering work in run-time reconfigurable FPGA design. We have developed an automated tool flow to accomplish micro-reconfiguration (a fast method for reconfiguring small parts of the FPGA at run-time) tailored to implement a parametrized application. In this novel approach, the infrequently changing input values of a design - called its parameters - are implemented as constants and the design is optimized for these constants. When the input parameter values change, the design is re-optimized for the new constant values by reconfiguring the FPGA. This way, we use specialized (constant) calculation blocks (such as multipliers) instead of generic functions (multiplications) with bulky generic blocks that consume a substantial amount of FPGA resources. This can reduce the FPGA resource utilization and can thus improve the performance of the resulting design significantly.
2. FPGA Compilation (High-level Synthesis, Placement and Routing)
Many of the old compilation techniques are designed for single-core processors. It is hard to adapt these old techniques in order to exploit the acceleration potential of the multiple cores in the modern workstations. We have investigated the main runtime consuming parts of the old techniques and proposed new compilation techniques that can accelerate these parts by exploiting the multi-core processor environment. We propose new pack, placement and routing techniques that improve the runtime and quality. These efforts contribute to a shorter FPGA design cycle and a smaller divide between the academic and commercial results. Our new compilation tools have been made available to the academic community in an open source project which is implemented in Java.
3. On-chip Interconnection Networks
Interconnection networks play a crucial role in the design of high performance parallel processing computing platforms. NoCs are generally subject to stringent, and often conflicting, timing, power, area, and reliability constraints due to the continuous integration scale. Moreover, with the aggressive scaling of the VLSI technology, NoCs are rapidly becoming so complex that designing them to rely on static configurations will be prohibitively inefficient and insufficient. As a result, we focus on extending the design methodology of large-scale NoCs in order to develop systems which are able to continually adapt to changes and automatically orchestrate the network activities based on the underlying dynamic environment.
Completed Projects
EXTRA: Exploiting eXascale Technology with Reconfigurable Architectures
Period: 2015-09-01 to 2018-08-31
Funding: European Commission H2020 FETHPC2014, Project No. 671653
Synthesis and Mapping for Reconfigurable Connections on FPGA
Period: 2011-10-01 to 2013-09-30
Funding: Federaal Wetenschapsbeleid/Politique scientifique fédérale
Grant Number: 836060980
HELP Video!
Period: 2016-10-01 to 2018-09-30
Description: A platform for embedded, efficient, low Latency, and portable video processing
Funding: imec.icon research project funded by imec and Agentschap Innoveren & Ondernemen
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
Period: 2011-09-01 to 2015-08-31
Funding: European Commission FP7, Project No. 287804
Home-MATE: Home-compatible Multimodal Alarm Triggering for Epilepsy
Period: 2008-01-01 to 2015-10-31
Funding: GOA (Geconcerteerde OnderzoeksActie) project funded by Ghent University
ARCHIMEDES: Accelerometry and Reservoir Computing for Home-compatible Intelligent Multimodel Early Detection of Epileptic Seizures
Period: 2008-01-01 to 2014-10-31
Funding: Federaal Wetenschapsbeleid/Politique scientifique fédérale
Grant Number: 2172
Scholarship Brahim Al Farisi – Changing between functionalities during run-time using parameterized configurations
Period: 2011-01-01 to 2014-12-31
Funding: Federaal Wetenschapsbeleid/Politique scientifique fédérale
Grant Number: 2138270980
OptiMMA: Optimization of MP-SoC Middleware for Event-driven Applications
Period: 2008-01-01 to 2011-12-31
Funding: SBO (Strategic Basic Research) project funded by IWT
FlexWare: Exploitation of Flexible Hardware Platforms for Massively Parallel Bioinformatics Applications
Period: 2007-01-01 to 2010-12-31
Funding: IWT-sponsored SBO project
Intelligent Autonomous Systems with Built-in Digital Spiking Neural Network
Period: 2005-01-01 to 2008-12-31
Funding: FWO project, Project No. G.0317.05
Measuring and Preventing Side-channel Information Leakage in Integrated Circuits
Period: 2005-01-01 to 2008-12-31
Funding: FWO project, Project No. G.0475.05
PICMOS: Photonic Interconnect Layer on CMOS by Waferscale Integration
Period: 2004-01-01 to 2006-12-31
Funding: EU FP6 IST STReP, Project No. FP6-2002-IST-1-002131
RESUME: Reconfigurable Embedded Systems for Use in Scalable Multimedia Environments
Period: 2003-01-01 to 2006-12-31
Funding: IWT-sponsored GBOU project
Reconfigurable Hardware for Embedded Systems
Period: 2003-01-01 to 2006-12-31
Funding: FWO project, Project No. G.0021.03
Interconnection-based Design Methodology for Systems-on-a-Chip
Period: 2003-02-01 to 2005-01-31
Funding: UGent-BOF VEO project
Embedded Systems for Multimedia Applications Toward an Efficient Design Methodology
Period: 2003-02-01 to 2005-01-31
Funding: UGent-BOF GOA project
IO: Interconnect by Optics
Period: 2001-09-01 to 2004-08-01
Funding: EU Research Framework Programme EU-RFP5, Project No. 00.0539-2
Boraflex
Funding: IWT O&O project with Siemens & HoGent