Paper Accepted in Micro and Nanostructures
Our paper “Modeling and Optimization of CFET Structures for Sub-3 nm CMOS Scaling” by Nour El I Boukortt and Dirk Stroobandt has been accepted for publication in Micro and Nanostructures (Elsevier).
Abstract
As semiconductor scaling approaches the sub-3 nm regime, conventional FinFET architectures face increasing challenges in controlling short-channel effects (SCEs) while maintaining power–performance–area (PPA) efficiency. Complementary FET (CFET) architectures, which vertically integrate nFET and pFET devices, offer improved electrostatic control and a reduced footprint, making them strong candidates for next-generation logic technologies.
In this study, three-dimensional FinFET and CFET structures with a 15 nm gate length are modeled and calibrated using experimental data from IBM and TSMC via TCAD tools. After validation, the models are employed to systematically examine the impact of fin width, fin height, gate length, source/drain extension length, and gate stack engineering on both DC and RF performance. Key metrics including threshold voltage (Vth), subthreshold slope (SS), drain-induced barrier lowering (DIBL), and RF characteristics are analyzed.
Publication Details
- Authors: Nour El I Boukortt, Dirk Stroobandt
- Journal: Micro and Nanostructures
- Publisher: Elsevier
- Publication Date: November 30, 2025
- Pages: 208506