1. Run-time Reconfiguration
Our group is world-renowned for its pioneering work in run-time reconfigurable FPGA design. We have developed an automated tool flow to accomplish micro-reconfiguration (a fast method for reconfiguring small parts of the FPGA at run-time) tailored to implement a parametrized application. In this novel approach, the infrequently changing input values of a design - called its parameters - are implemented as constants and the design is optimized for these constants. When the input parameter values change, the design is re-optimized for the new constant values by reconfiguring the FPGA. This way, we use specialized (constant) calculation blocks (such as multipliers) instead of generic functions (multiplications) with bulky generic blocks that consume a substantial amount of FPGA resources. This can reduce the FPGA resource utilization and can thus improve the performance of the resulting design significantly.
2. FPGA Compilation (High-level Synthesis, Placement and Routing)
Many of the old compilation techniques are designed for single-core processors. It is hard to adapt these old techniques in order to exploit the acceleration potential of the multiple cores in the modern workstations. We have investigated the main runtime consuming parts of the old techniques and proposed new compilation techniques that can accelerate these parts by exploiting the multi-core processor environment. We propose new pack, placement and routing techniques that improve the runtime and quality. These efforts contribute to a shorter FPGA design cycle and a smaller divide between the academic and commercial results. Our new compilation tools have been made available to the academic community in an open source project which is implemented in Java.
3. On-chip Interconnection Networks
Interconnection networks play a crucial role in the design of high performance parallel processing computing platforms. NoCs are generally subject to stringent, and often conflicting, timing, power, area, and reliability constraints due to the continuous integration scale. Moreover, with the aggressive scaling of the VLSI technology, NoCs are rapidly becoming so complex that designing them to rely on static configurations will be prohibitively inefficient and insufficient. As a result, we focus on extending the design methodology of large-scale NoCs in order to develop systems which are able to continually adapt to changes and automatically orchestrate the network activities based on the underlying dynamic environment.
