Xiaoke is presently pursuing my Ph.D. studies within the UGent Hardware Embedded System (HES) team at the CSL lab, under the guidance of Prof. Dirk Stroobandt since Oct. 2023. He obtained his MSc in Electrical Engineering from Ghent University in 2023.
His current research focuses on interconnect-aware EDA (logic synthesis and physical design) — especially optimizing netlist interconnect structure to accelerate FPGA physical design and resolve interconnect bottlenecks in 2.5D/3D FPGA systems.