HES group presents at DAC '15

HES group will attend the Design Automation Conference 2015 in San Fransisco.

We will be presenting a poster in the Work-in-Progress track with the title "Towards Efficient Hardware Debugging using Parameterized FPGA Reconfiguration" by Alexia Kourfali.

In this paper we propose a low overhead debugging method, which is entirely automated and integrated within the normal FPGA CAD flow. The main (parameterised) debugging infrastructure is presented, which is meant for both emulation approaches (for ASIC verification) and on-line in field debugging approaches (for FPGA design verification) and it includes increasing design observability. This infrastructure lies within the circuit implementation and is only invoked when a debugging parameter is set. Therefore, this infrastructure is always present but does not require much additional area. The area needed is found by introducing parameterised reconfiguration in the application. Hence, thanks to the fact that there is virtually no overhead over the original implementation, we can add the debugging functionality for free.

We will also present a paper in the Technical Program with the title "Avoiding Transitional Effects in Dynamic Circuit Specialisation on FPGAs" by Karel Heyse.

Dynamic Circuit Specialisation (DCS) is a technique that uses the reconfigurability of an FPGA to optimise a circuit during run-time, thus achieving higher performance and lower resource cost. However, run-time reconfiguration causes transitional effects that form an important problem for DCS. Because of these, the DCS circuit cannot be used while it is being reconfigured. This limits the usability of DCS for streaming applications and other applications that cannot tolerate downtime. For other applications, this results in a loss of performance.
In this paper, we present a technique to perform partial reconfiguration for DCS without transitional effects, thus allowing the circuit to remain fully functional at all times. The proposed method performs DCS by reconfiguring only LookUp Tables of the FPGA and does not require changes to the configuration architecture of the FPGA. The approach was tested and evaluated on current Xilinx FPGAs.