HES group leads European project on run-time reconfigurable computing
The Computer Systems Lab HES team (Hardware and Embedded Systems) of Ghent University will coordinate the EU-project "EXTRA: Exploiting eXascale Technology with Reconfigurable Architectures" within the European Horizon 2020 programme FETHPC (Future and Emerging Technologies Proactive programme Towards Exascale High Performance Computing). The project starts September 1, 2015 and runs for three years, with a total budget of almost 4 million euro and a planned 567 person months of work.
Prof. Dirk Stroobandt is the project coordinator of the EXTRA project, involving also universities from the UK (Imperial College London and University of Cambridge), Greece (Telecommunications Systems Institute), Italy (Politecnico di Milano), the Netherlands (Universiteit van Amsterdam) and Germany (Ruhr-Universität Bochum), as well as companies from Greece (Synelixis) and the UK (Maxeler).
In the EXTRA project, we propose to create a new and flexible exploration platform for developing reconfigurable architectures and tools with run-time reconfiguration built-in from the start. The idea is to enable the joint optimization of architecture, tools, applications and reconfiguration technology in order to prepare for the necessary power-efficient HPC hardware nodes of the future. This includes:
- Using novel reconfiguration approaches for processing, BRAMs, special blocks and interconnection. These reconfiguration approaches allow speeding up the reconfiguration process and having targeted reconfiguration for specific reconfigurable functions.
- A reconfigurable coarse grain architecture with as basic components processing, memory, and interconnection units of different complexity. The basic components can be those provided by current FPGAs but the system will also incorporate more complex components like basic CPUs, switches, caches that will also be instantiated and/or reconfigured on demand; those can be built-in or implemented on reconfigurable fabric.
- Just-in-time synthesis methods for reconfiguration on the fly. The whole system can be synthesized/reconfigured based on immediate application requirements. This requires a complete tool flow that targets this just-in-time synthesis. We aim at reducing the reconfiguration time so as to make reconfiguration more useful.
- Optimizations of applications with reconfiguration as an explicit design concept.
- The complete chain from device up to the application.
As part of our project, we offer the European research community a research platform with open source architecture descriptions and tools for continued research on reconfiguration and for finding the next-generation system requirements (a virtual tool environment – such as VPR). We want to provide the European platform for run-time reconfiguration to maintain Europe’s competitive edge and leadership in run-time reconfiguration and reconfigurable computing.