Alexandra Kourfali and Amit Kulkarni present at DAC on a Richard Newton Young Student Fellow Award.

The two newest Ph.D. students in the Hardware and Embedded Systems (HES) team of Ghent University, Alexandra Kourfali and Amit Kulkarni, had the opportunity to present a poster at DAC, the largest conference in their research field, through the Richard Newton Young Student Fellow Award.

The Design Automation Conference (DAC) celebrated its 50th anniversary in June 2013. In honor of the memory of Dr. Richard Newton, the 50th Design Automation Conference sponsored an expanded Young Student Fellow Program. It is designed to assist young students at the beginning of a career in Electronic Design Automation and Embedded Systems.

The Newton Fellows received a travel grant and full conference registration in order to actively participate in the 50th Design Automation Conference in Austin Texas. They had the opportunity to participate in numerous activities during the conference, including meetings with design automation luminaries, attendance at technical sessions and exhibits. The main  goal for this program was to learn how to make use of a conference, build the network with the industry & academic people and get exposed to the new technology trends.

Alexandra and Amit presented a poster during the DAC student event and PhD Forum.  

Alexandra presented her work on Fault Emulation using Dynamic FPGA Reconfiguration. She proposed a novel Fault Emulation technique introducing an FPGA-based approach for the evaluation of the fault tolerance of combinational circuits. The technique builds on the Parameterized Reconfigurations tool flow, developed by the HES group. The technique has been developed for Dynamic Circuit Specialization (DCS) and is now applied forefficient  test set generation. The goal is to achieve a speedup over the mainstream fault simulation but without the implications caused by using the fault emulation techniques.

Amit presented his current research work on a run-time reconfigurable VCGRA (Virtual Coarse Grain Reconfigurable Array) tool flow and the evaluation of the DCS tool flow on different FPGAs. The main use of the VCGRA tool flow is to obtain a specialized bit stream. In order to generalize this process the standard VPR tool will be adopted for VCGRAs. Amit will also work on the evaulation of the DCS tool flow. Critical parameters of DCS such as micro-reconfiguration time, overhead and memory etc.. will be evaluated and compared during the execution of the DCS tool on various families of Xilinx FPGAs such as Virtex2Pro, Virtex5 and the 7 series on the Zed Board.